The present invention relates in general to programmable logic devices and in particular to a field programmable logic module for flexibly interconnecting several digital logic devices.
Manufacturers of mass produced electronic equipment often use application specific integrated circuits (ASICs) to implement complex logic requirements. An ASIC can efficiently implement very large scale logic circuits in a small package, but an ASIC requires much time and money to develop. When large quantities of an ASIC are needed, the development cost may be relatively small on a per unit basis, but when only a few copies of an ASIC are needed, per unit development costs can be prohibitive. Also, the specific logic circuit implemented by an ASIC is fixed in the ASIC during fabrication and cannot be changed. Thus when a product change requires even a small change in the logic implemented by an ASIC, the ASIC must be redesigned and refabricated.
Field programmable logic devices (FPLDs) overcome some of the cost, time and inflexibility problems associated with using ASICs to implement logic circuitry. An FPLD is an integrated circuit which, like an ASIC, performs logic operations on one or more input signals to produce one or more output signals. However, an FPLD can be programmed by externally generated programming signals to implement user-specified digital logic operations. FPLDs are often used in place of ASICs in prototype equipment and in equipment produced in limited quantities. FPLDs are also used to implement logic circuits that are expected to change. Early embodiments of the concept include programmable array logic devices (PALs) and programmable logic devices (PLDs). PALs and PLDs serve as a convenient means for integrating a small number (typically 5 to 10) of small or medium scale integrated devices. In recent years, a new variety of programmable logic device, the Field Programmable Gate Array (FPGA) offering a much higher capacity (thousands of gates) and architectural flexibility, has gained wide popularity among designers.
While FPLDs are less expensive and more flexible than ASICs, they are also less efficient; they cannot implement in a single package as complex a logic circuit as an ASIC. When a block of logic is too large to implement in a single FPLD, a designer can partition the logic block into smaller blocks, each of which may be implemented by a separate programmable logic device or other components. However, the problem of interconnecting separate FPLDs often proves very troublesome. When a designer implements a logic block using several FPLDs, the designer must create a circuit board to interconnect them. Circuit boards are inflexible and time-consuming to manufacture. A change to the design of a logic system implemented by a set of interconnected FPLDs may require fabrication of a new circuit board. Thus the advantage of being able to quickly modify and test various designs of a logic block implemented by FPLDs may be lost when the designer is forced to fabricate new circuit boards to interconnect them.
One solution is to impose severe restrictions on the permissible partitions of the logic block so as not to disturb the interconnections between FPLDs implementing the block. However, this is undesirable because it places unnecessary limitations on the design.
U.S. Pat. No. 5,036,473 entitled "METHOD OF USING ELECTRONICALLY RECONFIGURABLE LOGIC CIRCUITS", issued Jul. 30, 1991 to Butts et al, attempts to solve the problems of both implementing and interconnecting blocks of logic of a prototype circuit by providing a circuit board on which several FPLDs and programmable crossbar switches are permanently mounted. There are also sockets for mounting other circuit components such as custom integrated circuits that may be supplied by a user.
A crossbar switch has several I/O pins and can be programmed by an externally generated programming signal to route data signals arriving on any one I/O pin to any other I/O pin. In the Butts et al system, the I/O pins of the crossbar switches are connected to one another and to the I/O ports of the FPLDs and user device sockets in a distributed fashion. By properly programming the crossbar switches, an I/O port of any FPLD or user supplied device can be connected to an I/O port of any other FPLD or to any other I/O port of any user-supplied device mounted on the board. With this system, when change to a block of logic implemented by FPLDs requires changes in interconnections therebetween, the interconnection changes can be quickly and easily handled by reprogramming the crossbar switches. No change in circuit board hardware is required.
Crossbar switches of the prior art may be either active or passive. An "active" crossbar switch includes buffers that actively drive signals at its output I/O pins in response to signals at its input I/O pins. Active buffering ensures that the signals are not degraded as they pass through the crossbar switches between FPLDs. A "passive" crossbar switch simply passes signals between its I/O pins without buffering. Passive crossbar switches can accommodate either unidirectional or bi-directional signals, but since the signals must pass through unidirectional buffers, prior art active crossbar switches can only accommodate unidirectional signals.
Butts et al disclose active buffering to interconnect FPLDs and user supplied components mounted on the board. A problem arises when the block of logic to be implemented includes bi-directional buses. Butts et al suggest either avoiding bi-directional buses by partitioning bi-directional buses into two unidirectional buses (FIGS. 13 and 14) or using logic or gating in the crossbar switch to enable buffers in the crossbar switch (FIGS. 15 and 16). In the former case, the devices being interconnected must have an input and an output terminal because the "bi-directional" bus is actually two unidirectional buses. In the latter case, the devices being interconnected by a true bi-directional bus must supply the crossbar switch with an enable signal input indicating direction of signal flow.
These methods solve the problem of actively buffering "bi-directional" signals passing between components only when the designer has control over the implementation of the devices being interconnected. The designer must ensure that such devices have only unidirectional inputs and outputs or that the devices supply an extra direction indicating enable signal with each bi-directional input/output signal. In cases where the logic is entirely implemented by FPLDs, the designer does have such control over device implementation. However, in many cases the user may wish to interconnect existing integrated circuits that have true bi-directional input/output buses but do not provide output direction indicating enable signals. In such situation, the Butts et al system is unable to provide actively buffered bi-directional interfaces between circuit components.